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features ? single 2.7 - 3.6v supply rapids ? serial interface: 40 mhz maximum clock frequency (spi modes 0 and 3 compatible for frequencies up to 33 mhz) page program ? 8192 pages (528 bytes/page) automated erase operations ? page erase 528 bytes ? block erase 4,224 bytes two 528-byte sram data buffers ? allows receiving of data while reprogramming the flash array continuous read capability through entire array ? ideal for code shadowing applications low-power dissipation ? 10 ma active read current typical ? 6 a standby current typical hardware and software data protection features ? individual sector locking security: 128-byte security register ? 64-byte user programmable space ? unique 64-byte device identifier jedec standard manufacturer and device id read 100,000 program/erase cycles per page minimum data retention ? 20 years commercial and industrial temperature ranges green (pb/halide-free/rohs co mpliant) packaging options 1. description the at45db321c is an spi compatible, serial-interface flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data- storage applications. the at45db321c supports a 4-wire serial interface known as rapids for applications requiring very high speed operations. its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. in addition to the 33-megabit main memory, the at45db321c also contains two sram buffers of 528 bytes each. the buffers allow the receiving of data while a page in the main page memory is being reprogrammed, as well as writing a continuous data stream. eeprom emulation (bit or byte alterability) is eas ily handled with a self-contained three step read -modify-write operation. unlike conventional flash memories that are accessed randomly with mul- tiple address lines and a parallel interface, the dataflash uses a rapids serial interface to sequentially access its data. the simple sequential access dramatically reduces active pin count, facilitates hardwa re layout, increases system reliability, min- imizes switching noise, and reduces packag e size. the device is optimized for use in many commercial and industri al applications where high-density, low-pin count, low- voltage and low-power are essential. the device operates at clock frequencies up to 40 mhz with a typical active read current consumption of 10 ma. 32-megabit 2.7 volt dataflash ? at45db321c 3387l?dflash?6/06
2 3387l?dflash?6/06 at45db321c to allow for simple in-system reprogrammabi lity, the at45db321c does not require high input voltages for programming. the device operates from a single power supply, 2.7v to 3.6v, for both the program and read operations. the at45db321c is enabled through the chip select pin (cs ) and accessed via a three-wire interface consisting of the serial input (si), serial output (so), and the serial clock (sck). all programming and erase cycles are self-timed. 2. pin configurations and packages table 2-1. pin configurations pin name function cs chip select sck serial clock si serial input so serial output wp hardware page write protect pin reset chip reset rdy/busy ready/busy figure 2-1. tsop top view ? type 1 figure 2-2. cbga top view through package figure 2-3. soic top view figure 2-4. dataflash card (1) top view through package note: 1. see at45dcb004c datasheet figure 2-5. cason ? top view through package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 rdy/busy reset wp nc nc vcc gnd nc nc nc cs sck si so nc nc nc nc nc nc nc nc nc nc nc nc nc nc a b c d e 1 2345 nc nc nc nc nc vcc wp reset nc nc gnd rdy/bsy si nc nc sck cs so nc nc nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2 8 27 26 25 24 23 22 21 20 19 1 8 17 16 15 g n d n c n c cs sck si so n c n c n c n c n c n c n c v cc n c n c w p reset rdy/busy n c n c n c n c n c n c n c n c 76 54321 si sck reset cs so gnd vcc wp 8 7 6 5 1 2 3 4
3 3387l?dflash?6/06 at45db321c 3. block diagram 4. memory array to provide optimal flexibility, t he memory array of the at45db321c is divided into three levels of granularity comprising of sectors, blocks, and pages. the ?memory architecture diagram? illus- trates the breakdown of each level and details t he number of pages per sector and block. all program operations to the dataflash occur on a page by page basis. the erase operations can be performed at the block or page level. figure 4-1. memory architecture diagram flash memory array page (528 bytes) buffer 2 (528 bytes) buffer 1 (528 bytes) i/o interface sck cs reset vcc gnd rdy/busy wp so si sector 0a = 8 pages 4224 bytes (4k + 128) sector 0b = 504 pages 266,112 bytes (252k + 8064) block = 4224 bytes (4k + 128) 8 pages sector 0a sector 0b page = 528 bytes (512 + 16) page 0 page 1 page 6 page 7 page 8 page 9 page 8190 page 8191 block 0 page 14 page 15 page 16 page 17 page 18 page 8189 block 1 sector architecture block architecture page architecture block 0 block 1 block 62 block 63 block 64 block 65 block 1022 block 1023 block 126 block 127 block 128 block 129 sector 1 sector 15 = 512 pages 270,336 bytes (256k + 8k) block 2 sector 1 = 512 pages 270,336 bytes (256k + 8k) sector 14 = 512 pages 270,336 bytes (256k + 8k) sector 2 = 512 pages 270,336 bytes (256k + 8k)
4 3387l?dflash?6/06 at45db321c 5. device operation the device operation is controlled by instructions from the host processor. the list of instructions and their associated opcodes are contained in tables 1 through 4. a valid instruction starts with the falling edge of cs followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. while the cs pin is low, toggling the sck pin controls the loading of the opcode and the desired buffer or main memory address location through the si (serial input) pin. all instructions, addresses, and data are transferred with the most significant bit (msb) first. buffer addressing is referenced in the datasheet using the terminology bfa9-bfa0 to denote the 10 address bits required to designate a byte address within a buffer. main memory address- ing is referenced using the terminology pa12-pa0 and ba9-ba0, where pa12-pa0 denotes the 13 address bits required to designate a page ad dress and ba9-ba0 denotes the 10 address bits required to designate a byte address within the page. 5.1 read commands by specifying the appropriate opcode, data can be read from the main memory or from either one of the two sram data buffers. the dataflash supports rapids protocol for mode 0 and mode 3. please refer to the ?detailed bit-level read timing? diagrams in this datasheet for details on the clock cycle sequences for each mode. 5.1.1 continuous array read by supplying an initial starting address for the main memory array, the continuous array read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. the dataflash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. to perform a continuous read, an opcode of e8h must be clocked into the device. the opcode is followed by three address bytes (which comprises 24-bit page and byte address se quence) and 32 don?t care clock cycles. the first bit of the 24-bit address sequence is reserved for upward and downward compatib ility to larger and smaller den- sity devices (see the notes under section 13.6 on page 25 . the next 13 bits (pa12-pa0) of the 24-bit address sequence specify which page of the main memory array to read, and the last 10 bits (ba9-ba0) of the 24-bit address sequence specify the starting byte address within the page. the 32 don?t care clock cycles that follow the four address bytes are ne eded to initialize the read operation. following the don?t care clock cycles, additional clock pulses on the sck pin will result in data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data. when the end of a page in main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading ba ck at the beginning of the firs t page of memory. as with cross- ing over page boundaries, no de lays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operat ion and tristate the output pin (so). the maximum sck frequency allowable for t he continuous array read is defined by the f car specification. the continuous array read bypasses both data buffers and leaves the con- tents of the buffers unchanged.
5 3387l?dflash?6/06 at45db321c 5.1.2 main memory page read a main memory page read allows the user to read data directly from any one of the 8192 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. to start a page read, an opcode of d2h must be clocked into the device. the opcode is followed by three address bytes (which comprise 24-bit page and byte address sequence) and 32 don?t care clock cycles. the fi rst bit of the 24-bit address sequence is a reserved bit, the next 13 bits (pa12-pa0) of the 24-bit address sequence specify the page in main memory to be read, and the last 10 bits (ba9-ba0) of the 24-bit address sequence specify the starting byte address within that page. the 32 don?t care clock cycles that follow the three address bytes are sent to initialize the read opera tion. following the don?t care bytes, additional pulses on sck result in data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data. when the end of a page in main memory is reached, the device will continue reading back at the beginning of the same page. a low-to-high transition on the cs pin will terminate the read operation and tristate the output pin (so). the maximum sck frequency allowable for the main memory page read is defined by the f sck specification. the main memory page read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.1.3 buffer read data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. an opcode of d4h is used to read data from buffer 1, and an opcode of d6h is used to read data from buffer 2. to perform a buffer read, the opcode must be clocked into the device followed by three address bytes comprised of 14 don?t care bits and 10 buffer address bits (bfa9-bfa0). following the three address bytes, an additional don?t care byte must be clocked in to initialize the read operation. since the buffer size is 528 bytes, 10 buffer address bits are required to specify the first byte of data to be read from the buffer. the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data . when the end of a buffer is reached, the device will c ontinue reading back at the beginning of the buffer. a low-to-high transition on the cs pin will terminate the read operation and tristate the output pin (so). 5.2 program and erase commands 5.2.1 buffer write data can be clocked in from the si pin into either buffer 1 or buffer 2. to load data into either buffer, a 1-byte opcode, 84h for buffer 1 or 87h for buffer 2, must be clocked into the device, fol- lowed by three address bytes comprised of 14 don?t care bits and 10 buffer address bits (bfa9- bfa0). the 10 buffer address bits specify the first byte in the buffer to be written. after the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. if the end of the data buffer is reach ed, the device will wrap ar ound back to the beginning of the buffer. data will continue to be loaded in to the buffer until a low-to-high transition is detected on the cs pin.
6 3387l?dflash?6/06 at45db321c 5.2.2 buffer to main memory page program with built-in erase: data written into either buffer 1 or buffer 2 can be programmed into the main memory. to start the operation, an 8-bit opcode, 83h for buffer 1 or 86h for buffer 2, must be clocked into the device followed by three address bytes consisting of one reserved bit, 13 page address bits (pa12-pa0) that specify the page in the main memory to be written and 10 don?t care bits. when a low-to-high transition occurs on the cs pin, the part will first erase the selected page in main memory (the erased state is a logic 1) and then program the data stored in the buffer into the specified page in main memory. both the erase and the programming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the status register and the rdy/busy pin will indicate that the part is busy. 5.2.3 buffer to main memory page program without built-in erase a previously-erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. to start the operation, an 8-bit opcode, 88h for buffer 1 or 89h for buffer 2, must be clocked into the device followed by th ree address bytes consisting of one reserved bit, 13 page address bits (pa12-pa0) that specify the page in the main memory to be written and 10 don?t care bits. when a low-to-high transition occurs on the cs pin, the part will program the data stored in the buffer into the specified page in the main memory. it is necessary that the page in main memory that is being programmed has been previously erased using one of the erase commands (page erase or block erase). t he programming of the page is internally self- timed and should take place in a maximum time of t p . during this time, the status register and the rdy/busy pin will indicate that the part is busy. 5.2.4 page erase the page erase command can be used to individually erase any page in the main memory array allowing the buffer to main memory page program without built-in erase comm and to be utilized at a later time. to perform a page erase, an opcode of 81h must be loaded into the device, fol- lowed by three address bytes comprised of one reserved bit, 13 page address bits (pa12-pa0) that specify the page in the main memory to be erased and 10 don?t care bits. when a low-to- high transition occurs on the cs pin, the part will erase the select ed page (the eras ed state is a logic 1). the erase operation is internally self-timed and should take place in a maximum time of t pe . during this time, the status register and the rdy/busy pin will indicate that the part is busy. 5.2.5 block erase a block of eight pages can be erased at one time. this command is useful when large amounts of data has to be written into the device. th is will avoid using mult iple page erase commands. to perform a block erase, an opcode of 50h must be loaded into the device, followed by three address bytes comprised of one reserved bit, 10 page address bits (pa12-pa3) and 13 don?t care bits. the 10 page address bits are used to specify which block of eight pages is to be erased. when a low-to-high transition occurs on the cs pin, the part will erase the selected block of eight pages. the erase operation is internally self-timed and should take place in a max- imum time of t be . during this time, the status register and the rdy/busy pin will indicate that the part is busy.
7 3387l?dflash?6/06 at45db321c 5.2.6 main memory page program through buffer this operation is a combination of the buffer write and buffer to main memory page program with built-in erase operations. data is first clocked into buffer 1 or buffer 2 from the input pin (si) and then programmed into a specified page in the main memory. to initiate the operation, an 8-bit opcode, 82h for buffer 1 or 85h for buffer 2, must first be clocked into the device, followed by three address bytes. the address bytes are comprised of one reserved bit, 13 page address bits (pa12-pa0) that select the page in the main memory where data is to be written, and 10 buffer address bits (bfa9-bfa0) that select the first byte in the buffer to be written. after all address bytes are clocked in, the part will take data from the input pins and st ore it in the speci- fied data buffer. if the end of the buffer is re ached, the device will wrap around back to the beginning of the buffer. when there is a low-to-high transition on the cs pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into that memory page. both the erase and the programming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the status register and the rdy/busy pin will indicate that the part is busy. 5.3 additional commands 5.3.1 main memory page to buffer transfer a page of data can be transferred from the main memory to either buffer 1 or buffer 2. to start the operation, a 1-byte opcode, 53h for buffer 1 and 55h for buffer 2, must be clocked into the device, followed by three address bytes comprised of one reserved bit, 13 page address bits (pa12- pa0), which specify the page in main memory that is to be transferred, and 10 don?t care bits. the cs pin must be low while toggling the sck pin to load the opcode and the address bytes from the input pin (si). the transfer of the page of data from the main memory to the buffer will begin when the cs pin transitions from a low to a high state. during the transfer of a page of data (t xfr ), the status register can be read to determine whether the transfer has been com- pleted or not. table 5-1. block erase addressing pa12 pa 11 pa10 pa9 pa8 pa 7 pa6 pa5 pa4 pa3 pa2 pa1 pa 0 blo ck 0000000000xxx 0 0000000001xxx 1 0000000010xxx 2 0000000011xxx 3 1111111100xxx1020 1111111101xxx1021 1111111110xxx1022 1111111111xxx1023
8 3387l?dflash?6/06 at45db321c 5.3.2 main memory page to buffer compare a page of data in main memory can be compared to the data in buffer 1 or buffer 2. to initiate the operation, an 8-bit opcode, 60h for buffer 1 and 61h for buffer 2, must be followed by 24 address bits consisting of one reserved bit, 13 address bits (pa12 - pa0) which specify the page in the main memory that is to be compared to the buffer, and ten don?t care bits. the cs pin must be low while toggling the sck pin to load the opcode, the address bits, and the don?t care bits from the si pin. on the low-to-high transition of the cs pin, the 528 bytes in the selected main memory page will be compared with the 528 bytes in buffer 1 or buffer 2. during this time (t xfr ), the status register will indicate that the part is busy. on completion of the com- pare operation, bit 6 of the status register is updated with the result of the compare. 5.3.3 auto page rewrite this mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion. this mode is a combination of two operations: main memory page to buffer transfer and buffer to main memory page program with built-in erase. a page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. to start the rewrite oper- ation, a 1-byte opcode, 58h for buffer 1 or 59h for buffer 2, must be clocked into the device, followed by three address bytes comprised of one reserved bit, 13 page address bits (pa12-pa0) that specify the page in main memory to be rewritten and 10 don?t care bits. when a low-to-high transition occurs on the cs pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. the operation is internally self-timed and should take place in a maximum time of t ep . during this time, the status register and the rdy/busy pin will indicate that the part is busy. if a sector is programmed or reprogrammed sequentially page by page, then the programming algorithm shown in figure 15-1 on page 31 is recommended. otherwise, if multiple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in figure 15-2 on page 32 is recommended. each page within a sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations in that sector. 5.3.4 status register read the status register can be used to determine the device?s ready/busy status, the result of a main memory page to buffer compare operation, or whether the sector protection has been enabled. to read the status register, an opcode of d7h must be loaded into the device. after the opcode and optional dummy by te is clocked in, the 1-byte status re gister will be clocked out on the out- put pin (so), starting with the next clock cycle. for applications over 25 mhz, the opcode must be always followed with a dummy (don?t care) byte. the data in the status register, starting with the msb (bit 7), will be clocked out on the so pin during the next eight clock cycles. the most-significant bits of the status register will contain device informa tion, while the remain- ing least-significant bit is reversed for future use and will have undefined value. after the one byte of the status register has been clocked out, the sequence will repeat itself (as long as cs remains low and sck is being toggled). the data in the status register is constantly updated, so each repeating sequence will output new data. ready/busy status is indicated using bit 7 of the st atus register. if bit 7 is a 1, then the device is not busy and is ready to accept the next command. if bit 7 is a 0, then the device is in a busy state. there are many operations that can cause the device to be in a busy state: main memory page to buffer transfer, buffer to main memory page program with built-in erase, buffer to
9 3387l?dflash?6/06 at45db321c main memory page program without built-in erase, page erase, block erase, main memory page program, and auto page rewrite. bit 1 in the status register is used to provide information to the user whether or not the sector protection has been enabled or disabled, either by software-controlled method or hardware-con- trolled method. a logic 1 indicates that sector protection has been enabled and logic 0 indicates that sector protection has been disabled. the device density is indicated using bits 5, 4, 3, and 2 of the status register. for the at45db321c, the four bits are 1,1, 0, 1. the decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of dataflash devices. the device density is not the same as the density code indicated in the jedec device id information. the device density is prov ided only for backward compatibility. the result of the most recent main memory page to buffer compare operation is indicated using bit 6 of the status register. if bit 6 is a 0, then the data in the main memory page matches the data in the buffer. if bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. 6. sector protection two protection methods, hardware and software controlled, are provided. the selection of which sectors to be protected/unprotected from program and erase operations is defined in the sector protection register. 6.1 software sector protection sectors specified for protection in the sector protection register can be protected from program and erase operations by issuing the enable sector protection command. to enable the sector protection using the software controlled method, the cs pin must first be asserted as it would be with any other command. once the cs pin has been asserted, the appropriate 4-byte command sequence must be clocked in via the input pin (si). after the last bit of the command sequence has been clocked in, the cs pin must be deasserted after which the sector protection will be enabled. to disable the sector protection using the software controlled method, the cs pin must first be asserted as it would be with any other command. once the cs pin has been asserted, the appropriate 4-byte sequence for the disable sector protection command must be clocked in via the input pin (si). after the last bit of the command sequence has been clocked in, the cs pin must be deasserted after which the sector protection will be disabled. the disable sector pro- tection command is ignored while the wp pin is asserted. table 5-2. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdy/busy comp 1 1 0 1 protect x command byte 1 byte 2 byte 3 byte 4 enable sector protection 3dh 2ah 7fh a9h disable sector protection 3dh 2ah 7fh 9ah read sector protection register 32h 00h 00h 00h
10 3387l?dflash?6/06 at45db321c software sector protection is useful in applications in which the wp pin is not or cannot be con- trolled by a host processor. in such instances, the wp pin may be left floating (the wp pin is pulled high internally) and sector protection can be controlled using the software commands. if the device is power cycled, then the software sector protection will be disabled. once the device is powered up, the enable sector protecti on command should be reissued if sector pro- tection is desired and if the wp pin is not used. the reset pin has no effect on the software sector protection. 6.2 hardware sector protection sectors specified for protection in sector pr otection register can be protected from program and erase operations by utilizing the write protection (wp ) pin. the protection can be enabled by asserting the wp pin and keeping the pin in its asserted state. any sector specified for pro- tection cannot be erased or reprogrammed as long as the wp pin is asserted. the protection can be disabled by deasserting the wp pin high. a filter is provided on the wp pin to help protect against spurious noise on the wp pin. hardware sector protection will provide continuous pro- tection, based on the contents of the sector pr otection register, in an application where wp is always driven low. please read ?write protect (wp)? on page 15 for more information. 6.3 sector protection register sector protection register is a nonvolatile regi ster that contains 16 bytes of data, as shown below: note: 1. default value for devices shipped from atmel is 00h. sector number 0 (0a, 0b) 1 to 15 protected see below ffh unprotected 00h table 6-1. sector 0 (0a, 0b): 0a (page 0-7) 0b (page 8-511) bit 0, 1 data value bit 6, 7 bit 4, 5 bit 2, 3 sectors 0a, 0b unprotected 00 00 00 00 00h protect sector 0a (page 0-7) 11 00 00 00 c0h protect sector 0b (page 8-511) 00 11 11 00 3ch protect sectors 0a, 0b (page 0-511) 11 11 11 00 fch
11 3387l?dflash?6/06 at45db321c 6.3.1 erasing the sector protection register to erase the sector protection register, the cs pin must first be asserted. once the cs pin has been asserted, the 4-byte erase command sequence must be clocked in via the si (serial input) pin. after the last bit of the command sequence has been clocked in, the cs pin must be deas- serted to initiate the intern ally self-timed erase cycle (t pe ). the ready/busy status will indicate that the device is busy during the erase cycle. the erased state of each bit (of a byte) in the sec- tor protection register indicates that the corresponding sector is flagged for protection. the reset pin is disabled during this erase cycle to prevent incomplete erasure of the sector pro- tection register. 6.3.2 programming the sector protection register to program the sector protection register, the cs pin must first be asserted. once the cs pin has been asserted, the 4-byte command sequence must be clocked in via the si (serial input) pin. after the last bit of the command sequence has been clocked in, the data for the contents of the sector protection register must be clocked in. the first byte corresponds to sector 0 (0a, 0b), the second byte corresponds to sector 1 and the last byte (byte 16) corresponds to sector 15. after the last bit of data has been clocked in, the cs pin must be deasserted to initiate the internally self-timed program cycle (t p ). the ready/busy status will indicate that the device is busy during the program cycle. the reset pin is disabled during this program cycle to prevent incomplete programming of the sector protection register. 6.3.3 reading the sector protection register to read the sector protection register, the cs pin must first be asserted. once the cs pin has been asserted, a 4-byte comma nd sequence 32h, 00h, 00h, 00h and 32 don?t care clock cycles must be clocked in via the si (serial input) pin. the 32 don?t care clock cycles are required to ini- tialize the read operation. after the 32 don?t care clock cycles, any additional clock pulses on the sck pin will result in data being output on the so (serial output) pin. the read will begin with byte_1 of the sector protection register for sector_0, followed with byte_2 for sector_1. the read operation will continue until byte_16 for sector_15 is read. once the last byte is read a low- to-high transition on the cs pin is required to terminate the read operation. note: next generation devices of the ?d? family will not require the 32 don?t care clock cycles. command byte 1 byte 2 byte 3 byte 4 erase sector protection register 3dh 2ah 7fh cfh command byte 1 byte 2 byte 3 byte 4 program sector protection register 3dh 2ah 7fh fch command byte 1 byte 2 byte 3 byte 4 read sector protection register 32h 00h 00h 00h
12 3387l?dflash?6/06 at45db321c 6.3.4 various aspects about the sector protection register due to the sharing of the internal circuitry, the contents of t he buffer 1 will get modified during the erase and programming of sector protection register. if the device is powered down during erasing or programming the sector protection register, then the contents of the sector protection register cannot be guaranteed. the sector protection register can be erased or reprogrammed with the sector protection enabled or disabled. being able to reprogram the sector protection register with the sector protection enabled allows the user to temporarily disable the sector pro- tection to an individual sector rather than disabling the sector protection completely. the sector protection register is subject to the same endurance characteristics as the main memory array. users are encouraged to carefully evaluate the number of times the sector pro- tection register will be modified du ring the course of the applicatio ns? life cycle. if the application requires that the sector protection register be modified more than the specified endurance of the dataflash because the application needs to temporarily unprotect individual sectors (sector protection remains enabled while the sector protection register is reprogrammed), then the application will need to limit this practice. instead, a combination of temporarily unp rotecting indi- vidual sectors alon g with disabling sector protection completely will need to be implemented by the application to ensure that the endurance limits of the device are not exceeded.
13 3387l?dflash?6/06 at45db321c 7. manufacturer and device id read this instruction conforms to the jedec standard and allo ws the user to read the manufacturer id, device id, and extended device information. a 1-byte opcode, 9fh, must be clocked into the device while the cs pin is low. after the opcode is clocked in, th e manufacturer id, 2 bytes of device id and exten ded device information w ill be clocked out on the so pin. the fourth byte of the sequence output is the extended device information string length byte. this byte is used to signify how many bytes of extended device informatio n will be output. 7.1 manufacturer and device id information note: based on jedec publication 106 (jep106), ma nufacturer id data can be comprised of any number of bytes. some manufacturers may have manufacturer id codes that are two, three or even four byte s long with the first byte(s) in the sequence being 7fh. a system sh ould detect code 7fh as a ?continuation code? and continue to read manufacturer id bytes. the first non-7fh byte w ould signify the last byte of manufacturer id data. for atmel (and some other manufacturers), the manufacturer id data is comprised of only one byte. 7.1.1 byte 1 ? manufacturer id hex value jedec assigned code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1fh 0 0 0 1 1 1 1 1 manufacturer id 1fh = atmel 7.1.2 byte 2 ? device id (part 1) hex value family code density code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 family code 001 = dataflash 27h 0 0 1 0 0 1 1 1 density code 00111 = 32-mbit 7.1.3 byte 3 ? device id (part 2) hex value mlc code product version code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mlc code 000 = 1-bit/cell technology 00h 0 0 0 0 0 0 0 0 product version 00000 = initial version 7.1.4 byte 4 ? extended device information string length hex value byte count bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h 0 0 0 0 0 0 0 0 byte count 00h = 0 bytes of information 9fh manufacturer id byte n device id byte 1 device id byte 2 this information would only be output if the extended device information string length value was something other than 00h. extended device information string length extended device information byte x extended device information byte x + 1 cs 1fh 27h 00h 00h data data si so opcode each transition represents 8 bits and 8 clock cycles
14 3387l?dflash?6/06 at45db321c 7.2 security register the at45db321c contains a specialized register th at can be used for security purposes in sys- tem design. the security register is a unique 128-b yte register that is divided into two portions. the first 64 bytes (byte 0 to byte 63) of this page are allocated as a one-time user programmable space. once these 64 bytes have been programmed, they should not be reprogrammed. the remaining 64 bytes of this page (byte 64 to byte 127) are fa ctory programmed by atmel and will contain a unique number for each device. the factory programmed data is fixed and cannot be changed. the security register can be read by clocking in a 4-byte sequence 77h, 00h, 00h, 00h to the device followed by 32 don?t care clock cycles. see the opcode table 9-4 on page 20 . note: next generation devices of the ?d? family will not require the 32 don?t care clock cycles. to program the first 64 bytes of the security register, a two step sequence must be used. the first step requires that the user loads the desired data into buffer 1 by using the buffer 1 write operation (opcode 84h ? ?buffer write? on page 5 ). the user should specify the starting buffer address as location zero and should write a full 64 bytes of information into the buffer. other- wise, the first 64 bytes of the buffer may contain data that was previously stored in the buffer. it is not necessary to fill the remaining 464 bytes (byte locations 64 through 527) of the buffer with data. after the buffer 1 write operation has been completed, the security register can be sub- sequently programmed by reselecting the device and clocking in opcode 9ah into the device followed by three don?t care bytes (24 clock cycl es). after the final don?t care clock cycle has been completed, a low-to-high transition on the cs pin will cause the device to initiate an inter- nally self-timed program operation in which the contents of buffer 1 will be pr ogrammed into the security register. only the first 64 bytes of data in buffer 1 will be prog rammed into the security register; the remaining 464 byte s of the buffer will be ignored. the security register program operation should take place in a maximum time of t p . 7.3 operation m ode summary the modes described can be separated into two groups ? modes that make use of the flash memory array (group a) and modes that do not make use of the flash memory array (group b). group a modes consist of: 1. main memory page read 2. continuous array read 3. main memory page to buffer 1 (or 2) transfer 4. main memory page to buffer 1 (or 2) compare 5. buffer 1 (or 2) to main memory page program with built-in erase 6. buffer 1 (or 2) to main memory page program without built-in erase 7. main memory page program through buffer 1 (or 2) 8. page erase 9. block erase 10. auto page rewrite group b modes consist of: 1. buffer 1 (or 2) read 2. buffer 1 (or 2) write 3. status register read 4. manufacturer and device id read
15 3387l?dflash?6/06 at45db321c if a group a mode is in progress (not fully completed), then another mode in group a should not be started. however, during this time in which a group a mode is in progress, modes in group b can be started, except the first two group a commands (memory array read commands). this gives the dataflash the ability to virtually accommodate a continuo us data stream. while data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). see application note an-4 (?usin g atmel?s serial dataflash?) for more details. 7.4 pin descriptions 7.4.1 serial input (si) the si pin is an input-only pin and is used to shi ft data serially into the device. the si pin is used for all data input, including opcodes and address sequences. 7.4.2 serial output (so) the so pin is an output-only pin and is used to shift data serially out from the device. 7.4.3 serial clock (sck) the sck pin is an input-only pin and is used to control the flow of data to and from the dataflash. data is always clocked into the device on the rising edge of sck and clocked out of the device on the falling edge of sck. 7.4.4 chip select (cs ) the dataflash is selected when the cs pin is low. when the device is not selected, data will not be accepted on the input pin (s i), and the output pin (so) will re main in a high impedance state. a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transi- tion on the cs pin is required to end an operation or to start an internally self-timed operation. 7.4.5 write protect (wp ) the wp pin is used to control the hardware sector protection. hardware sector protection is enabled by asserting the wp pin and keeping the pin in it?s asserted state. disabling hardware sector protection is accomplished by simply deasserting the wp pin. the wp pin will override the software controlled sector protection method but only for protecting the sectors. for exam- ple, if the sectors were not previously protected by the enable sector protection command, then simply asserting the wp pin for the minimum specified time (t wpe ) would enable the sector pro- tection. when the wp pin is deasserted; however, the sector protection would no longer be enabled as long as the enable sector protection command was not issued while the wp pin was asserted. if the enable sector protection command was issued before or while the wp pin was asserted, then simply deasserting the wp pin would not disable the sector protection. in this case, the disable sector protection command would need to be issued while the wp pin is deasserted to disable the sector protection. the disable sector protection command is also ignored whenever the wp pin is asserted. to ensure backwards com patibility with previous ge nerations of dataflash, the function of the wp pin has not changed. therefore, when the wp pin is asserted, certai n sectors in the memory array will be protected, and when the wp pin is deasserted, the memory array will be unpro- tected provided the enable sector protection command hasn?t been issued. new devices are shipped from atmel with the contents of the sector protection register pre-programmed with ?00h? (unprotect). the user can reprogram the sector protection register to change which sec- tors will be protected by the wp pin.
16 3387l?dflash?6/06 at45db321c the table below details the sector protection status for various scenarios of the wp pin, the enable sector protection command, and the disable sector protection command. 7.4.6 reset a low state on the reset pin (reset ) will terminate the operation in progress and re set the inter- nal state machine to an id le state. the device will remain in the reset condi tion as long as a low level is present on the reset pin. normal operation can resume once the reset pin is brought back to a high level. the device incorporates an internal power-on reset circuit, so there are no restrictions on the reset pin during power-on sequences. the reset pin is also internally pulled high; therefore, in low pin count applications, connection of the reset pin is not necessary if this pin and fea- ture will not be utilized. however, it is recommended that the reset pin be driven high externally whenever possible. 7.4.7 ready/busy this open drain output pin will be driven low when the device is busy in an internally self-timed operation. this pin, which is no rmally in a high state (through an external pull-up resistor), will be pulled low during programming/erase operations, and page-to-buffer transfers. the busy status indicates that the flash memory array and one of the buffers cannot be accessed; read and writ e operations to the ot her buffer can still be performed. during page erase and block erase, read and write operations can be performed to both buffers. wp 123 time period wp pin enable sector protection command disable se ctor protection command sector protection status 1 high high high command not issued previously command issued ? x ? command issued disabled enabled disabled 2 low x x enabled 3 high high high command issued during period 1 or 2 ? issue command not issued yet command issued ? enabled disabled enabled
17 3387l?dflash?6/06 at45db321c 8. power-on/reset state when power is first applied to the device, or when recovering from a reset condition, the device will default to mode 3. in additi on, the output pin (so) will be in a high impedance state, and a high-to-low transition on the cs pin will be required to start a va lid instruction. the mode (mode 3 or mode 0) will be automatically selected on every falling edge of cs by sampling the inactive clock state. after power is applied and v cc is at the minimum datasheet value, the system should wait 20 ms before an operational mode (dataflash) is started. 9. system considerations the rapids serial interface is controlled by the serial clock sck, serial input si and chip select cs pins. these signals must rise and fall monoto nically and be free from noise. excessive noise or ringing on these pins can be misinterpreted as multiple edges and cause improper operation of the device. the pc board traces must be kept to a minimum distance or appropriately termi- nated to ensure proper operation. if necessary, decoupling capacitors can be added on these pins to provide filtering against noise glitches. as system complexity continues to increase, voltage regulation is becoming more important. a key element of any voltage regulation scheme is its current sourcing capability. like all flash memories, the peak current for dataflash occur during the programming and erase operation. the regulator needs to supply this peak current requirement. an under specified regulator can cause current starvation. besides increasing sy stem noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. for applications that require random modificati ons of data within a sector, please refer to ?auto page rewrite? on page 8 . atmel c generation dataflash utilizes a sophisti cated adaptive algorithm during erase and pro- gramming to maximize the endurance over the life of the device. the algorithm uses a verification mechanism to check if the memory cells have been erased or programmed success- fully. if the memory cells were not erased or programmed completely, the algorithm erases or programs the memory cells again. the process will continue until the device is erased or pro- grammed successfully. in order to optimize the erase and programming time, fixed timing should not be used. instead, the rdy/busy bit of the status register or the rdy/busy pin should be monitored.
18 3387l?dflash?6/06 at45db321c note: 1. legacy opcodes 52h, 54h, 56h, 57h, and 68h are still s upported for reasons of backward compatibility only and are not recommended for new designs. the inactive clock polarity high or low modes will not be supported in the future products. table 9-1. read commands command sck mode opcode continuous array read rapids mode 0 or 3 e8h inactive clock polarity low or high 68h main memory page read rapids mode 0 or 3 d2h inactive clock polarity low or high 52h buffer 1 read rapids mode 0 or 3 d4h inactive clock polarity low or high 54h buffer 2 read rapids mode 0 or 3 d6h inactive clock polarity low or high 56h status register read rapids mode 0 or 3 d7h inactive clock polarity low or high 57h manufacturer and device id rapids mode 0 or 3 9fh table 9-2. program and erase commands command sck mode opcode buffer 1 write mode 0, mode 3 84h buffer 2 write mode 0, mode 3 87h buffer 1 to main memory page program with built-in erase mode 0, mode 3 83h buffer 2 to main memory page program with built-in erase mode 0, mode 3 86h buffer 1 to main memory page program without built-in erase mode 0, mode 3 88h buffer 2 to main memory page program without built-in erase mode 0, mode 3 89h page erase mode 0, mode 3 81h block erase mode 0, mode 3 50h main memory page program through buffer 1 mode 0, mode 3 82h main memory page program through buffer 2 mode 0, mode 3 85h
19 3387l?dflash?6/06 at45db321c notes: 1. this command should be used for applications requ iring a high number of random page writes within a sector. see ?auto page rewrite? on page 8. 2. the security register program command util izes data stored in buffer 1. therefore, this command must be used in conjunc- tion with the buffer 1 write command. see ?security register? on page 14 for details. table 9-3. additional commands command sck mode opcode main memory page to buffer 1 transfer mode 0, mode 3 53h main memory page to buffer 2 transfer mode 0, mode 3 55h main memory page to buffer 1 compare mode 0, mode 3 60h main memory page to buffer 2 compare mode 0, mode 3 61h auto page rewrite through buffer 1 (1) mode 0, mode 3 58h auto page rewrite through buffer 2 (1) mode 0, mode 3 59h security register program (2) mode 0, mode 3 9ah security register read mode 0, mode 3 77h
20 3387l?dflash?6/06 at45db321c note: r = reserved bit, p = page address bit, b = byte/buffer address bit, x = don?t care table 9-4. detailed bit-level addressing sequence opcode opcode address byte address byte address byte additional don?t care bytes required 50h 01010000 r pppppppppp xxxxxxxxxxxxx n/a 52h 01010010 r ppppppppppppp bbbbbbbbbb 4 bytes 53h 01010011 r ppppppppppppp xxxxxxxxxx n/a 54h 01010100 x xxxxxxxxxxxxx bbbbbbbbbb 1 byte 55h 01010101 r ppppppppppppp xxxxxxxxxx n/a 56h 01010110 x xxxxxxxxxxxxx bbbbbbbbbb 1 byte 57h 01010111 n/a n/a n/a n/a 58h 01011000 r ppppppppppppp xxxxxxxxxx n/a 59h 01011001 r ppppppppppppp xxxxxxxxxx n/a 60h 01100000 r pppppppppppppx x x xxxxxxx n/a 61h 01100001 r pppppppppppppx x x xxxxxxx n/a 68h 01101000 r ppppppppppppp bbbbbbbbbb 4 bytes 77h 01110111 0 0 0000000000000000000000 4 81h 10000001 r ppppppppppppp xxxxxxxxxx n/a 82h 10000010 r ppppppppppppp bbbbbbbbbb n/a 83h 10000011 r ppppppppppppp xxxxxxxxxx n/a 84h 10000100 x xxxxxxxxxxxxx bbbbbbbbbb n/a 85h 10000101 r ppppppppppppp bbbbbbbbbb n/a 86h 10000110 r ppppppppppppp xxxxxxxxxx n/a 87h 10000111 x xxxxxxxxxxxxx bbbbbbbbbb n/a 88h 10001000 r ppppppppppppp xxxxxxxxxx n/a 89h 10001001 r ppppppppppppp xxxxxxxxxx n/a 9ah 10011010 x xxxxxxxxxxxxxxxxxxxxxxx n/a 9fh 10011111 n/a n/a n/a n/a d2h 11010010 r ppppppppppppp bbbbbbbbbb 4 d4h 11010100 x xxxxxxxxxxxxx bbbbbbbbbb 1 d6h 11010110 x xxxxxxxxxxxxx bbbbbbbbbb 1 d7h 11010111 n/a n/a n/a 1/0 e8h 11101000 r ppppppppppppp bbbbbbbbbb 4 r eserve d pa 12 pa 1 1 pa 1 0 pa 9 pa 8 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 ba9 ba8 ba 7 ba 6 ba 5 ba4 ba3 ba2 ba 1 ba 0
21 3387l?dflash?6/06 at45db321c 10. electrical specifications note: 1. after power is applied and v cc is at the minimum specified da tasheet value, the system should wait 20 ms before an opera- tional mode is started. notes: 1. i sb maximum specification limit is tested at 3.3v and 70 c. 2. i cc1 during a buffer read is 30 ma maximum. 3. i cc1 changes typically by 300 a per 1 mhz change in clock frequency. 4. all inputs are 5 volts tolerant. table 10-1. absolute maximum ratings* temperature under bias .... ........... ............ ..... -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v table 10-2. dc and ac operating range at45db321c operating temperature (case) com. 0 c to 70 c ind. -40 c to 85 c v cc power supply (1) 2.7v to 3.6v table 10-3. dc characteristics symbol parameter condition min typ max units i sb (1) standby current cs , reset , wp = v ih , all inputs at cmos levels 615a i cc1 (2)(3) active current, read operation, serial interface f = 20 mhz; i out = 0 ma; v cc = 3.6v 10 15 ma i cc2 active current, program operation, page program v cc = 3.6v 35 50 ma i cc3 active current, page erase operation v cc = 3.6v 30 40 ma i cc4 active current, block erase operation v cc = 3.6v 30 40 ma i li input load current v in = cmos levels 1 a i lo output leakage current v i/o = cmos levels 1 a v il input low voltage v cc x 0.3 v v ih input high voltage v cc x 0.7 v v ol output low voltage i ol = 1.6 ma; v cc = 2.7v 0.4 v v oh output high voltage i oh = -100 a v cc - 0.2v v
22 3387l?dflash?6/06 at45db321c note: 1. maximum specified frequency for spi compatibility is 33 mhz. 2. the device uses an adaptive algorithm during program and erase operations. use the rdy/busy bit of the status register or the rdy/busy pin to determine whether the program or erase opera tion has completed. fixed timing should not be used. 3. value are based on device characterization, not 100% tested in production. table 10-4. ac characteristics ? serial interface symbol parameter min typ max units f sck (1) sck frequency 40 mhz f car (1) sck frequency for continuous array read 40 mhz t wh sck high time 10 ns t wl sck low time 10 ns t cs minimum cs high time 250 ns t css cs setup time 100 ns t csh cs hold time 250 ns t csb cs high to rdy/busy low 150 ns t su data in setup time 3 ns t h data in hold time 6 ns t ho output hold time 0 ns t dis output disable time 10 ns t v output valid 12 ns t xfr page to buffer transfer/compare time 350 s t ep (2)(3) page erase and programming time 16 50 ms t p (2)(3) page programming time 8 15 ms t pe (2)(3) page erase time 8 35 ms t be (2)(3) block erase time 20 100 ms t rst reset pulse width 10 s t rec reset recovery time 1 s t wpe wp low to protection enabled 1 s t wpd wp high to protection disabled 1 s
23 3387l?dflash?6/06 at45db321c 11. input test waveform s and measurement levels t r , t f < 2 ns (10% to 90%) 12. output test load 13. ac waveforms four different timing waveforms are shown below. waveform 1 shows the sck signal being low when cs makes a high-to-low transition, and wa veform 2 shows the sck signal being high when cs makes a high-to-low transition. in both cases, output so becomes valid while the sck signal is still low (sck low time is specified as t wl ). timing waveforms 1 and 2 conform to rap- ids serial interface but for frequencies up to 33 mhz and are compatible with spi mode 0 and spi mode 3 respectively. waveforms 1 and 2 are also compatible with inactive clock polarity low and inactive clock polarity high, since the maxi mum specified frequency in that case is 33 mhz. waveform 3 and waveform 4 illustra te general timing diagram for r apids serial interface. these are similar to waveform 1 and waveform 2, except that output so is not restricted to become valid during the t wl period. these timing waveforms are valid over the full frequency range (max- imum frequency = 40 mhz) of the rapids serial case. 13.1 waveform 1 ? spi mode 0 compat ible (for frequencies up to 33 mhz) ac driving levels ac measurement level 0v 1.5v 3.0v device under test 30 pf cs sck si so t css valid in t h t su t wh t wl t csh t cs t v high impedance valid out t ho t dis high impedance
24 3387l?dflash?6/06 at45db321c 13.2 waveform 2 ? spi mode 3 compat ible (for frequencies up to 33 mhz) 13.3 waveform 3 ? rapids m ode 0 (for all frequencies) 13.4 waveform 4 ? rapids m ode 3 (for all frequencies) cs sck so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high impedance si cs sck si so t css valid in t h t su t wh t wl t csh t cs t v high impedance valid out t ho t dis high impedance cs sck so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high impedance si
25 3387l?dflash?6/06 at45db321c 13.5 reset timing note: the cs signal should be in th e high state before the reset signal is deasserted. 13.6 command sequence for read/write operat ions (except status register read) notes: 1. ?r? designates bits rese rved for larger densities. 2. it is recommended that ?r? be a logical ?0 ? for densities of 32m bits or smaller. 3. for densities larger than 32m bits, the ?r? bit becomes the most significant page address bit for the appropriate density. cs sck reset so high impedance high impedance si t rst t rec t css si cmd 8 bits 8 bits 8 bits msb reserved for larger densities page address (pa12-pa0) byte/buffer address (ba9-ba0/bfa9-bfa0) lsb r x x x x x x x x x x x x x x x x x x x x x x x
26 3387l?dflash?6/06 at45db321c 14. write operations the following block diagram and waveforms illustra te the various write sequences available. 14.1 main memory page pr ogram through buffers 14.2 buffer write 14.3 buffer to main memory page program (dat a from buffer progra mmed into flash page) flash memory array page (528 bytes) buffer 2 (528 bytes) buffer 1 (528 bytes) i/o interface si buffer 1 to main memory page program main memory page program through buffer 2 buffer 2 to main memory page program main memory page program through buffer 1 buffer 1 write buffer 2 write si cmd n n+1 last byte completes writing into selected buffer starts self-timed erase/program operation cs r, pa12-6 pa5-0, bfa9-8 bfa7-0 si cmd x xx, bfa9-8 bfa7-0 n n+1 last byte completes writing into selected buffer cs si cmd pa5-0, xx x cs starts self-timed erase/program operation r , pa12-6 each transition represents 8 bits and 8 clock cycles n = 1st byte write n+1 = 2nd byte write
27 3387l?dflash?6/06 at45db321c 15. read operations the following block diagram and waveforms illustra te the various read sequences available. 15.1 main memory page read 15.2 main memory page to buffer transfer (data from flash page read into buffer) 15.3 buffer read flash memory array page (528 bytes) buffer 2 (528 bytes) buffer 1 (528 bytes) i/o interface main memory page to buffer 1 main memory page to buffer 2 main memory page read buffer 1 read buffer 2 read so si cmd pa5-0, ba9-8 ba7-0 x xxx cs n n+1 so r , pa12-6 si cmd pa5-0, xx x starts reading page data into buffer cs so r , pa12-6 si cmd x xx, bfa9-8 bfa7-0 cs n n+1 so x each transition represents 8 bits and 8 clock cycles n = 1st byte read n+1 = 2nd byte read
28 3387l?dflash?6/06 at45db321c 15.4 detailed bit-level read timing ? rapids serial interface mode 0 15.4.1 continuous array read (opcode: e8h) 15.4.2 main memory page read (opcode: d2h) 15.4.3 buffer read (opcode: d4h or d6h) si 1 1xxx cs so sck 12 62 63 64 65 66 67 high impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 data out bit 0 of page n+1 bit 4223 of page n lsb msb t su t v si 1 1 0 10 xxx cs so sck 12345 60 61 62 63 64 65 66 67 xx high impedance command opcode t su d 7 d 6 d 5 data out msb t v d 4 si 1 1 0 10 xxx cs so sck 12345 36 37 38 39 40 41 42 43 xx high impedance command opcode t su d 7 d 6 d 5 data out msb t v d 4
29 3387l?dflash?6/06 at45db321c 15.4.4 status register read (opcode: d7h) 15.4.5 manufacturer and device id read (opcode: 9fh) 15.5 detailed bit-level read timing ? rapids serial interface mode 3 15.5.1 continuous array read (opcode: e8h) si 1 1 0 10 111 cs so sck 12345 78910 11 12 15 16 high impedance status register output command opcode msb t su 6 d 1 d 0 d 7 lsb msb d 7 d 6 d 5 t v d 4 t v don?t care byte for freq. over 25 mhz si 1 0- 0 11 111 cs so sck 12345 78910 11 12 16 17 18 high impedance product id output command opcode msb t su 6 100 msb lsb 000 t v 1 manufacturer id si 1 1xxx cs so sck 12 63 64 65 66 67 high impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 bit 0 of page n+1 bit 4223 of page n lsb msb t su t v data out
30 3387l?dflash?6/06 at45db321c 15.5.2 main memory page read (opcode: d2h) 15.5.3 buffer read (opcode: d4h or d6h) 15.5.4 status register read (opcode: d7h) si 1 1 0 10 xxx cs so sck 12345 61 62 63 64 65 66 67 xx high impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 68 si 1 1 0 10 xxx cs so sck 12345 37 38 39 40 41 42 43 xx high impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 44 si 1 1 0 10 111 cs so sck 12345 78910 11 12 17 18 high impedance d 7 d 6 d 5 status register output command opcode msb t su t v 6 d 4 d 0 d 7 lsb msb d 6 t v don?t care byte for freq. over 25 mhz
31 3387l?dflash?6/06 at45db321c 15.5.5 manufacturer and device id read (opcode: 9fh) 15.6 auto page rewrite flowchart figure 15-1. algorithm for programming or reprogramming of the entire array sequentially notes: 1. this type of algorithm is used for applications in wh ich the entire array is programmed sequentially, filling the array page-by- page. 2. a page can be written using either a main memory page prog ram operation or a buffer write operation followed by a buffer to main memory page program operation. 3. the algorithm above shows the programming of a single page. the algorithm will be repeated sequentially for each page within the entire array. si 1 0 0 11 111 cs so sck 12345 78910 11 12 17 18 high impedance 000 product id output command opcode msb t su t v 6 110 lsb msb 0 manufacturer id start main memory page program through buffer (82h, 85h) end provide address and data buffer write (84h, 87h) buffer to main memory page program (83h, 86h)
32 3387l?dflash?6/06 at45db321c figure 15-2. algorithm for randomly modifying data notes: 1. to preserve data integrity, each page of a dataflash se ctor must be updated/rewritten at least once within every 10,000 cumulative page erase and program operations. 2. a page address pointer must be maintained to indicate which page is to be rewritten. the auto page rewrite command must use the address specified by the page address pointer. 3. other algorithms can be used to rewrite portions of the flash array. low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. see application note an-4 (?using atmel?s serial dataflash?) for more details. start main memory page to buffer transfer (53h, 55h) increment page address pointer (2) auto page rewrite (2) (58h, 59h) end provide address of page to modify if planning to modify multiple bytes currently stored within a page of the flash array main memory page program through buffer (82h, 85h) buffer write (84h, 87h) buffer to main memory page program (83h, 86h)
33 3387l?dflash?6/06 at45db321c 16. sector addressing pa12 pa1 1 pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa 2 - pa0 s e ct or 0000000000x 0a 0 0 00xxxxxx x 0b 0 0 01xxxxxx x 1 0 0 10xxxxxx x 2 1 1 00xxxxxx x 12 1 1 01xxxxxx x 13 1 1 10xxxxxx x 14 1 1 11xxxxxx x 15
34 3387l?dflash?6/06 at45db321c note: 1. not recommended for new designs. 17. ordering information f sck (mhz) i cc (ma) ordering code package operation range active standby 40 15 0.015 at45db321c-cc at45db321c-cnc at45db321c-tc 24c3 8cn3 28t commercial (0 c to 70 c) 40 15 0.015 at45db321c-ci at45db321c-ti 24c3 28t industrial (-40 c to 85 c) 18. green package options (pb /halide-free/rohs compliant) f sck (mhz) i cc (ma) ordering code package operation range active standby 40 15 0.015 at45db321c-cu at45db321c-cnu AT45DB321C-TU 24c3 8cn3 28t industrial (-40 c to 85 c) 19. legacy package options (1) f sck (mhz) i cc (ma) ordering code package operation range active standby 40 15 0.015 at45db321c-rc 28r commercial (0 c to 70 c) 40 15 0.015 at45db321c-ru 28r industrial (-40 c to 85 c) package type 24c3 24-ball (5 x 5 array), 1.0 mm pitch, 6 x 8 x 1.2 mm, plastic chip-scale ball grid array (cbga) 8cn3 8-pad (6 mm x 8 mm) chip array small outline no lead package (cason ) 28t 28-lead, plastic thin small outline package (tsop) 28r 28-lead, 0.330? wide, plastic gull wing small outline package (soic)
35 3387l?dflash?6/06 at45db321c 20. packaging information 20.1 24c3 ? cbga 2 3 25 orchard parkway s an jose, ca 951 3 1 title drawing no. r rev. 24c 3 , 24-ball (5 x 5 array), 1.0 mm pitch, 6 x 8 x 1.20 mm, chip-scale ball grid array package (cbga) a 24c 3 9/10/04 top view bottom view s ide view a b c d e 1.00 ref 2.00 ref e d a1 ball id 4 5 3 21 e1 d1 a a1 e e a1 ball corner ? b common dimen s ion s (unit of measure = mm) s ymbol min nom max note e 5.90 6.00 6.10 e1 4.0 typ d 7.90 8.00 8.10 d1 4.0 typ a ? ? 1.20 a1 0.25 ? ? e 1.00 b s c b 0.40 typ
36 3387l?dflash?6/06 at45db321c 20.2 8cn3 ? cason 2325 orch a rd p a rkw a y s a n jo s e, ca 95131 title drawing no. r rev. 8cn3, 8 -p a d (6 x 8 x 1.0 mm body), le a d pitch 1.27 mm, chip arr a y sm a ll o u tline no le a d p a ck a ge (cason) b 8 cn3 7/10/03 note s : 1. all dimen s ion s a nd toler a nce conform to asme y 14.5m, 1994. 2. the su rf a ce fini s h of the p a ck a ge s h a ll b e edm ch a rmille #24-27. 3. unle ss otherwi s e s pecified toler a nce: decim a l 0.05, ang u l a r 2 o . 4. met a l p a d dimen s ion s . common dimensions (unit of me asu re = mm) symbol min nom max note a 1.0 a1 0.17 0.21 0.25 b 0.41 typ 4 d 7.90 8 .00 8 .10 e 5.90 6.00 6.10 e 1.27 bsc e1 1.095 ref l 0.67 typ 4 l1 0.92 0.97 1.02 4 pin1 p a d corner m a rked pin1 indentifier 0.10 mm typ 4 3 2 1 5 6 7 8 top view l b e l1 e1 side view a1 a bottom view e d
37 3387l?dflash?6/06 at45db321c 20.3 28t ? tsop, type i 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28t , 28-lead (8 x 13.4 mm) plastic thin small outline package, type i (tsop) c 28t 12/06/02 pin 1 0o ~ 5o d1 d pin 1 identifier area b e e a a1 a2 c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-183. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.90 1.00 1.05 d 13.20 13.40 13.60 d1 11.70 11.80 11.90 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.55 basic
38 3387l?dflash?6/06 at45db321c 20.4 28r ? soic a 2. 3 9 ? 2.79 a1 0.050 ? 0. 3 56 d 18.00 ? 18.50 note 1 e 11.70 ? 12.50 e 1 8.59 ? 8.79 note 1 b 0. 3 56 ? 0.508 c 0.20 3 ? 0. 3 05 l 0.94 ? 1.27 e 1.27 typ pin 1 0o ~ 8o 2 3 25 orchard parkway s an jose, ca 951 3 1 title drawing no. r rev. 2 8 r, 28-lead, 0. 33 0" body width, plastic gull wing s mall outline ( s oic) c 28r 5/18/2004 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a e c a 1 e 1 e d l b note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
39 3387l?dflash?6/06 at45db321c 21. revision history revision level ? release date history l ? june 2006 added 28-lead soic pinout diagram on page 2.
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